{"id":130,"date":"2019-08-14T11:26:04","date_gmt":"2019-08-14T11:26:04","guid":{"rendered":"http:\/\/dsd.webs.upv.es\/?page_id=130"},"modified":"2025-08-06T16:23:44","modified_gmt":"2025-08-06T16:23:44","slug":"ejemplo-rtl","status":"publish","type":"page","link":"https:\/\/dsd.webs.upv.es\/?page_id=130","title":{"rendered":"Ejemplo RTL"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">Una de las dudas que suele surgirle a un dise\u00f1ador cuando maneja los arrays muldimensionales de SystemVerilog es si dichos c\u00f3digos son sintetizables.<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">Afortunadamente la mayor\u00eda de los sintetizadores de hoy en d\u00eda los admiten sin problemas. Para que sirva de ejemplo veamos el c\u00f3digo de un shifter 2D de 32 etapas de 8 bits<\/p>\n\n\n<div class=\"wp-block-syntaxhighlighter-code \"><pre class=\"brush: systemverilog; title: ; notranslate\" title=\"\">\nmodule shifter_2d(clock,reset,enable,clear,shift,entrada_serie, salida_serie);\nparameter tamanyo=32;\ninput clock; \/\/senyal de reloj\ninput reset; \/\/reset asincrono\ninput enable;\ninput &#x5B;7:0]entrada_serie;\ninput clear;\ninput shift;\noutput &#x5B;7:0] salida_serie ;\nlogic &#x5B;tamanyo-1:0]&#x5B;7:0] aux;\nalways_ff @(posedge clock or negedge reset)\nif (!reset)\n        aux&lt;={tamanyo{8&#039;b0}};\nelse\n\tif (!clear)\n\t\t\tif (shift==1&#039;b1)\n\t\t\t\taux&lt;={entrada_serie,aux&#x5B;tamanyo-1:1]};\n\telse\n\t\t\t\taux&lt;={tamanyo{8&#039;b0}};\nassign salida_serie=aux&#x5B;0];\nendmodule\n<\/pre><\/div>","protected":false},"excerpt":{"rendered":"<p>Una de las dudas que suele surgirle a un dise\u00f1ador cuando maneja los arrays muldimensionales de SystemVerilog es si dichos c\u00f3digos son sintetizables. Afortunadamente la mayor\u00eda de los sintetizadores de hoy en d\u00eda los admiten sin problemas. Para que sirva de ejemplo veamos el c\u00f3digo de un shifter 2D de 32 etapas de 8 bits<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":59,"menu_order":3,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_crdt_document":"","ub_ctt_via":"","footnotes":""},"class_list":["post-130","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/130","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=130"}],"version-history":[{"count":11,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/130\/revisions"}],"predecessor-version":[{"id":1833,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/130\/revisions\/1833"}],"up":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/59"}],"wp:attachment":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=130"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}