{"id":1569,"date":"2024-10-21T14:16:45","date_gmt":"2024-10-21T14:16:45","guid":{"rendered":"https:\/\/dsd.webs.upv.es\/?page_id=1569"},"modified":"2024-10-21T14:31:32","modified_gmt":"2024-10-21T14:31:32","slug":"manejo-basico-del-simulador","status":"publish","type":"page","link":"https:\/\/dsd.webs.upv.es\/?page_id=1569","title":{"rendered":"Manejo b\u00e1sico del simulador HDL"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\"><a href=\"https:\/\/poliformat.upv.es\/lessonbuilder-tool\/templates\/#\"><\/a><\/p>\n\n\n\n<p class=\"wp-block-paragraph\">En el siguiente v\u00eddeo podr\u00e9is observar:<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>C\u00f3mo arrancar la herramienta de manera aislada<\/li>\n\n\n\n<li>Como compilar y\u00a0simular el c\u00f3digo verilog\/systemverilog que teng\u00e1is entre manos<\/li>\n\n\n\n<li>C\u00f3mo visualizar los resultados (a trav\u00e9s de un visualizador de ondas)<\/li>\n\n\n\n<li>C\u00f3mo modificar las entradas de vuestro c\u00f3digo mediante comandos de la herramienta de tipo \u00abforce\u00bb. No es muy recomendable hacer esto para un dise\u00f1o (mejor construirte un banco de pruebas en verilog\/systemverilog) pero puede permitirte probar algo de manera muy r\u00e1pida<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-embed is-type-video is-provider-youtube wp-block-embed-youtube wp-embed-aspect-4-3 wp-has-aspect-ratio\"><div class=\"wp-block-embed__wrapper\">\n<iframe loading=\"lazy\" title=\"Simulaci\u00f3n RTL: arranque b\u00e1sico | 9\/34 | UPV\" width=\"960\" height=\"720\" src=\"https:\/\/www.youtube.com\/embed\/22sjDY1C3_w?feature=oembed\" frameborder=\"0\" allow=\"accelerometer; autoplay; clipboard-write; encrypted-media; gyroscope; picture-in-picture; web-share\" referrerpolicy=\"strict-origin-when-cross-origin\" allowfullscreen><\/iframe>\n<\/div><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>En el siguiente v\u00eddeo podr\u00e9is observar:<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ub_ctt_via":"","footnotes":""},"class_list":["post-1569","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/1569","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=1569"}],"version-history":[{"count":2,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/1569\/revisions"}],"predecessor-version":[{"id":1576,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/1569\/revisions\/1576"}],"wp:attachment":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=1569"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}