{"id":566,"date":"2020-11-12T10:23:58","date_gmt":"2020-11-12T10:23:58","guid":{"rendered":"http:\/\/dsd.webs.upv.es\/?page_id=566"},"modified":"2020-11-12T10:26:28","modified_gmt":"2020-11-12T10:26:28","slug":"diseno","status":"publish","type":"page","link":"https:\/\/dsd.webs.upv.es\/?page_id=566","title":{"rendered":"Dise\u00f1o"},"content":{"rendered":"\n<p class=\"wp-block-paragraph\">En este apartado vamos a recopilar estilo de dise\u00f1o RTL con SystemVerilog de ciertos subsistemas combinacionales y secuenciales de amplio uso<\/p>\n","protected":false},"excerpt":{"rendered":"<p>En este apartado vamos a recopilar estilo de dise\u00f1o RTL con SystemVerilog de ciertos subsistemas combinacionales y secuenciales de amplio uso<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":0,"menu_order":2,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ub_ctt_via":"","footnotes":""},"class_list":["post-566","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/566","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=566"}],"version-history":[{"count":1,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/566\/revisions"}],"predecessor-version":[{"id":567,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/566\/revisions\/567"}],"wp:attachment":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=566"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}