{"id":591,"date":"2020-11-12T14:04:44","date_gmt":"2020-11-12T14:04:44","guid":{"rendered":"http:\/\/dsd.webs.upv.es\/?page_id=591"},"modified":"2025-08-06T16:48:55","modified_gmt":"2025-08-06T16:48:55","slug":"memorias-rom","status":"publish","type":"page","link":"https:\/\/dsd.webs.upv.es\/?page_id=591","title":{"rendered":"Memorias ROM"},"content":{"rendered":"\n<h3 class=\"wp-block-heading\"><span class=\"has-inline-color has-vivid-cyan-blue-color\"><strong>ROM As\u00edncronas<\/strong><\/span><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Cambian el puerto de salida cuando cambia la direcci\u00f3n de lectura sin la necesidad de un flanco de reloj adicional<\/li>\n\n\n\n<li>La inferencia de memorias as\u00edncronas depende de la tecnolog\u00eda que se dispone. En la actualidad la mayor\u00eda de las memorias embebidas de los dispositivos programables son s\u00edncronas y esta inferencia de memorias as\u00edncronas (combinacionales sin reloj) deriva en una implementaci\u00f3n realizada con l\u00f3gica (LUTs)<\/li>\n<\/ul>\n\n\n<div class=\"wp-block-syntaxhighlighter-code \"><pre class=\"brush: systemverilog; title: ; notranslate\" title=\"\">\nmodule rom_asynch (address,dout);\nparameter d_width = 16;\nparameter a_width = 6;\ninput &#x5B;a_width-1:0] address;\noutput &#x5B;d_width-1:0] dout;\nlogic &#x5B;d_width-1:0] mem&#x5B;(1&amp;lt;&amp;lt;a_width)-1:0] ; \ninitial\n    $readmemh(&quot;pesos_2.dat&quot;, mem);\nassign dout = mem&#x5B;address];\nendmodule\n<\/pre><\/div>\n\n\n<h3 class=\"wp-block-heading\"><strong><span class=\"has-inline-color has-vivid-cyan-blue-color\">ROM S<\/span><\/strong><span class=\"has-inline-color has-vivid-cyan-blue-color\">\u00edncronas<\/span><\/h3>\n\n\n\n<ul id=\"block-9ca95c80-294f-4f67-8a29-24ef593e75d8\" class=\"wp-block-list\">\n<li>Cambian el puerto de salida cuando cambia la direcci\u00f3n de lectura siempre y cuando tengamos un flanco de reloj<\/li>\n\n\n\n<li>La inferencia de memorias s\u00edncronas es directa en memorias embebidas. Por ejemplo en un dispositivo como la Cyclone IV del laboratorio ser\u00eda mediante las memorias embebidas de 9kbits <\/li>\n<\/ul>\n\n\n\n<div class=\"wp-block-urvanov-syntax-highlighter-code-block\"><pre class=\"lang:verilog decode:true \">module rom_synch_in \n#(parameter DATA_WIDTH=32, parameter ADDR_WIDTH=7)\n(\n\tinput [(ADDR_WIDTH-1):0] addr,\n\tinput clk, \n\toutput logic [(DATA_WIDTH-1):0] q\n);\n\t\/\/ Declare the ROM variable\n\tlogic [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0];\n\tinitial\n\tbegin\n\t\t$readmemh(\"tanh_1.dat\", rom);\n\tend\n\talways_ff @ (posedge clk)\n\tbegin\n\t\tq &lt;= rom[addr];\n\tend\nendmodule\n<\/pre><\/div>\n\n\n<div class=\"wp-block-syntaxhighlighter-code \"><pre class=\"brush: systemverilog; title: ; notranslate\" title=\"\">\nmodule rom_synch_in \n#(parameter DATA_WIDTH=32, parameter ADDR_WIDTH=7)\n(\n\tinput &#x5B;(ADDR_WIDTH-1):0] addr,\n\tinput clk, \n\toutput logic &#x5B;(DATA_WIDTH-1):0] q\n);\n\t\/\/ Declare the ROM variable\n\tlogic &#x5B;DATA_WIDTH-1:0] rom&#x5B;2**ADDR_WIDTH-1:0];\n\tinitial\n\tbegin\n\t\t$readmemh(&quot;tanh_1.dat&quot;, rom);\n\tend\n\talways_ff @ (posedge clk)\n\tbegin\n\t\tq &amp;lt;= rom&#x5B;addr];\n\tend\nendmodule\n<\/pre><\/div>\n\n\n<h3 class=\"wp-block-heading\"><span class=\"has-inline-color has-vivid-cyan-blue-color\">Inicializaci\u00f3n de las ROM<\/span><\/h3>\n\n\n\n<p class=\"wp-block-paragraph\">Para aportar contenidos a la memoria utilizaremos \u201csystem tasks\u201d preestablecidos<\/p>\n\n\n\n<ul class=\"wp-block-list\">\n<li>$readmemb: Obtiene los contenidos de un fichero ASCII en donde los valores est\u00e1n escritos en formato binario<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"312\" height=\"276\" src=\"https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-5.png\" alt=\"\" class=\"wp-image-594\" style=\"width:227px;height:201px\" srcset=\"https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-5.png 312w, https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-5-300x265.png 300w\" sizes=\"auto, (max-width: 312px) 100vw, 312px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>$readmemh: Obtiene los contenidos de un fichero ASCII en donde los valores est\u00e1n escritos en formato hexadecimal<\/li>\n<\/ul>\n\n\n\n<figure class=\"wp-block-image size-large is-resized\"><img loading=\"lazy\" decoding=\"async\" width=\"274\" height=\"276\" src=\"https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-6.png\" alt=\"\" class=\"wp-image-595\" style=\"width:216px;height:218px\" srcset=\"https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-6.png 274w, https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-6-150x150.png 150w, https:\/\/dsd.webs.upv.es\/wp-content\/uploads\/2020\/11\/image-6-45x45.png 45w\" sizes=\"auto, (max-width: 274px) 100vw, 274px\" \/><\/figure>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Cuando se desea introducir una direcci\u00f3n, el formato utilizado es en hexadecimal en cualquiera de los casos .<\/li>\n\n\n\n<li>Suele llamarse a dichos procedimientos desde un initial como se ha visto en los ejemplos anteriores<\/li>\n\n\n\n<li>Aunque el fichero puede tener una extensi\u00f3n b\u00e1sica de .txt, es recomendable la utilizaci\u00f3n de la extensi\u00f3n .dat  <\/li>\n<\/ul>\n\n\n\n<p class=\"wp-block-paragraph\">La sintaxis completa de este tipo de \u00absystem task\u00bb es:<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><span class=\"has-inline-color has-vivid-red-color\"><strong>$readmemb<\/strong><\/span>(\u201c<em>&lt;file_name&gt;<\/em>\u201d, &lt;memory_name&gt;, &lt;start_addr&gt;?,&lt;finish_addr&gt;?);<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">siendo los dos \u00faltimos argumentos opcionales<\/p>\n","protected":false},"excerpt":{"rendered":"<p>ROM As\u00edncronas ROM S\u00edncronas module rom_synch_in #(parameter DATA_WIDTH=32, parameter ADDR_WIDTH=7) ( input [(ADDR_WIDTH-1):0] addr, input clk, output logic [(DATA_WIDTH-1):0] q ); \/\/ Declare the ROM variable logic [DATA_WIDTH-1:0] rom[2**ADDR_WIDTH-1:0]; initial begin $readmemh(\u00abtanh_1.dat\u00bb, rom); end always_ff @ (posedge clk) begin q &lt;= rom[addr]; end endmodule Inicializaci\u00f3n de las ROM Para aportar contenidos a la memoria utilizaremos \u201csystem tasks\u201d preestablecidos La sintaxis completa de este tipo de \u00absystem task\u00bb es: $readmemb(\u201c&lt;file_name&gt;\u201d, &lt;memory_name&gt;, &lt;start_addr&gt;?,&lt;finish_addr&gt;?); siendo los dos \u00faltimos argumentos opcionales<\/p>\n","protected":false},"author":2,"featured_media":0,"parent":568,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_crdt_document":"","ub_ctt_via":"","footnotes":""},"class_list":["post-591","page","type-page","status-publish","hentry"],"featured_image_src":null,"_links":{"self":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/591","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/users\/2"}],"replies":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=591"}],"version-history":[{"count":9,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/591\/revisions"}],"predecessor-version":[{"id":1857,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/591\/revisions\/1857"}],"up":[{"embeddable":true,"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=\/wp\/v2\/pages\/568"}],"wp:attachment":[{"href":"https:\/\/dsd.webs.upv.es\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=591"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}