El planteamiento de esta entrada es si podemos hacer una verificación física del RISC-V, en la placa DE2-115 mediante el LCD.
La controladora verilog de LCD proviene de la siguiente dirección y autoría:
https://gist.github.com/windhooked/40f6c9a6d35062a5d24503d2bcb07ddd
La adaptación que he realizado ha consistido fundamentalmente en generar una salida adicional que resetee el micro RISC-V mientras el LCD arranca, de forma que cuando esté el LCD inicializado, liberemos el micro RISC-V y pueda empezar a ejecutar sus instrucciones. Esa salida adicional se denomina RST_output.
Otro cambio que introduje fue un enable general denominado TC_general de un contador módulo 20 que nos garantice que los niveles a 1 de LCD_E sean superiores a 400 ns (trabajamos con un reloj de 50 MHz), aunque cómo veréis he multiplicado por 20 todas las temporizaciones y solo así he conseguido que funcionara.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 |
module FPGA_2_LCD_RAFA( CLK, LCD_RS, LCD_RW, LCD_E, LCD_DB, RDY, DATA, OPER, ENB, RST, RST_output ); input CLK; // For this code to work without modification, CLK should equal 24MHz input [7:0] DATA; // The Data to send to the LCD Module input [1:0] OPER; // The Type of operation to perform (data or instruction) input ENB; // Tells the module that the data is valid and start reading DATA and OPER input RST; output RDY; // Indicates that the module is Idle and ready to take more data output RST_output; output LCD_RS, LCD_RW, LCD_E; output [7:0] LCD_DB; reg RST_output; wire [7:0] DATA; wire [1:0] OPER; wire ENB; reg RDY; reg [7:0] LCD_DB=0; reg LCD_RW=0; // always write to (and never read from) the LCD reg LCD_RS=0; // HI means Data, LOW means Instruction/Command reg LCD_E=0; /*----------------------SOME NOTES------------------- when RS and R/W change STATE...wait for at least 20ns ( ~1clock cycle ) after that period of time bring E high and invert E every 400 ns (can be larger) ( ~20 clock cycles) while E is HI, set DATA when E goes LOW, maintain DATA for atleast 10ns CLOCK=50MHz ==> 20 ns -------------------------END OF NOTES-------------------*/ //=============================================================================================== //------------------------------Define the Timing Parameters------------------------------------- //=============================================================================================== parameter [19:0] t_40ns = 1; //20ns == ~1clk parameter [19:0] t_250ns = 6; //400ns == ~20clks parameter [19:0] t_42us = 1008; //21us == ~1008clks parameter [19:0] t_100us = 2400; //50us == ~2400clks parameter [19:0] t_1640us = 39360; //0.82ms == ~39360clks parameter [19:0] t_4100us = 98400; //2.05ms == ~98400clks parameter [19:0] t_15000us = 360000; //7,5ms == ~360000clks //=============================================================================================== //------------------------------Define the BASIC Command Set------------------------------------- //=============================================================================================== parameter [7:0] SETUP = 8'b00111000; //Execution time = 42us, sets to 8-bit interface, 2-line display, 5x7 dots parameter [7:0] DISP_ON = 8'b00001100; //Execution time = 42us, Turn ON Display parameter [7:0] ALL_ON = 8'b00001111; //Execution time = 42us, Turn ON All Display parameter [7:0] ALL_OFF = 8'b00001000; //Execution time = 42us, Turn OFF All Display parameter [7:0] CLEAR = 8'b00000001; //Execution time = 1.64ms, Clear Display parameter [7:0] ENTRY_N = 8'b00000110; //Execution time = 42us, Normal Entry, Cursor increments, Display is not shifted parameter [7:0] HOME = 8'b00000010; //Execution time = 1.64ms, Return Home parameter [7:0] C_SHIFT_L = 8'b00010000; //Execution time = 42us, Cursor Shift parameter [7:0] C_SHIFT_R = 8'b00010100; //Execution time = 42us, Cursor Shift parameter [7:0] D_SHIFT_L = 8'b00011000; //Execution time = 42us, Display Shift parameter [7:0] D_SHIFT_R = 8'b00011100; //Execution time = 42us, Display Shift //=============================================================================================== //-----------------------------Create the counting mechanisms------------------------------------ //=============================================================================================== reg [19:0] cnt_timer=0; //39360 clks, used to delay the STATEmachine during a command execution (SEE above command set) reg flag_250ns=0,flag_42us=0,flag_100us=0,flag_1640us=0,flag_4100us=0,flag_15000us=0; reg flag_rst=1; //Start with flag RST set. so that the counting has not started reg flag_40ns; reg [4:0] idea; wire TC_general; assign TC_general=(idea==5'b10011)?1'b1:1'b0; always @(posedge CLK, negedge RST) begin if (!RST) begin flag_40ns <=1'b0; flag_250ns <= 1'b0; //Unlatch the flag flag_42us <= 1'b0; //Unlatch the flag flag_100us <= 1'b0; //Unlatch the flag flag_1640us <= 1'b0; //Unlatch the flag flag_4100us <= 1'b0; //Unlatch the flag flag_15000us <= 1'b0; //Unlatch the flag cnt_timer <= 20'b0; idea<=5'b00000; end else begin if (idea==5'b10011) idea<=5'b00000; else idea<=idea+1; if (TC_general) if(flag_rst ) begin flag_40ns <=1'b0; flag_250ns <= 1'b0; //Unlatch the flag flag_42us <= 1'b0; //Unlatch the flag flag_100us <= 1'b0; //Unlatch the flag flag_1640us <= 1'b0; //Unlatch the flag flag_4100us <= 1'b0; //Unlatch the flag flag_15000us <= 1'b0; //Unlatch the flag cnt_timer <= 20'b0; end else begin flag_40ns<= cnt_timer[0]; //si el reloj es de 50 MHz , esta señal es de 25 MHz if(cnt_timer>=t_250ns) begin flag_250ns <= 1'b1; end else begin flag_250ns <= flag_250ns; end //---------------------------- if(cnt_timer>=t_42us) begin flag_42us <= 1'b1; end else begin flag_42us <= flag_42us; end //---------------------------- if(cnt_timer>=t_100us) begin flag_100us <= 1'b1; end else begin flag_100us <= flag_100us; end //---------------------------- if(cnt_timer>=t_1640us) begin flag_1640us <= 1'b1; end else begin flag_1640us <= flag_1640us; end //---------------------------- if(cnt_timer>=t_4100us) begin flag_4100us <= 1'b1; end else begin flag_4100us <= flag_4100us; end //---------------------------- if(cnt_timer>=t_15000us) begin flag_15000us <= 1'b1; end else begin flag_15000us <= flag_15000us; end //---------------------------- cnt_timer <= cnt_timer + 1; end end end //########################################################################################## //-----------------------------Create the STATE MACHINE------------------------------------ //########################################################################################## reg [3:0] STATE; reg [1:0] SUBSTATE; always @(posedge CLK, negedge RST) begin if (!RST) begin LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation LCD_E <= 1'b0; //We are in the initial setup, keep low until 250ns has past LCD_DB <= 8'b00000000; RDY <= 1'b0; //Indicate that the module is busy SUBSTATE <= 0; STATE<=0; flag_rst <= 1'b0; RST_output <=1'b0; end else if (TC_general) case(STATE) //--------------------------------------------------------------------------------------- 0: begin //---------------Initiate Command Sequence (RS=LOW)----------------------------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation LCD_E <= 1'b0; //We are in the initial setup, keep low until 250ns has past LCD_DB <= 8'b00000000; RDY <= 1'b0; //Indicate that the module is busy SUBSTATE <= 0; if(!flag_15000us) begin //WAIT 15ms...worst case scenario STATE <= STATE; //Remain in current STATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE flag_rst <= 1'b1; //Stop counting end end //--------------------------------------------------------------------------------------- 1: begin //-----------SET FUNCTION #1, 8-bit interface, 2-line display, 5x7 dots--------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= SETUP; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_4100us) begin //WAIT at least 4.1ms (required for Initialization) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 2: begin //-----------SET FUNCTION #2, 8-bit interface, 2-line display, 5x7 dots--------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= SETUP; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_100us) begin //WAIT at least 100us (required for Initialization) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 3: begin //-----------SET FUNCTION #3, 8-bit interface, 2-line display, 5x7 dots--------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= SETUP; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_100us) begin //WAIT at least 100us (required for Initialization) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 4: begin //-----------SET FUNCTION #4, 8-bit interface, 2-line display, 5x7 dots--------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= SETUP; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_100us) begin //WAIT at least 100us (required for Initialization) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 5: begin //-----------------DISPLAY, Display OFF, Cursor OFF, Blinking OFF------------------ LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= ALL_OFF; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_42us) begin //WAIT at least 42us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 6: begin //-------------------DISPLAY CLEAR, clear the display screen-------------------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= CLEAR; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_1640us) begin //WAIT at least 1640us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 7: begin //---------Normal ENTRY, Cursor increments, Display is not shifted-------------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= ENTRY_N; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_42us) begin //WAIT at least 42us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 8: begin //-----------------DISPLAY, Display ON, Cursor ON, Blinking ON------------------ LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= DISP_ON;//ALL_ON; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_42us) begin //WAIT at least 42us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 9: begin //-------------------DISPLAY CLEAR, clear the display screen-------------------- LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= CLEAR; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_1640us) begin //WAIT at least 1640us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= 15; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- 10: begin//----------------------------- WRITE DATA ------------------------------------- LCD_RS <= 1'b1; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; flag_rst <= 1'b1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= DATA; //WRITE THE CHARACTER if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(flag_250ns&& !flag_rst) begin STATE <= 15;//STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; end else begin //WAIT at least 250ns (required for LCD_E) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end end end //--------------------------------------------------------------------------------------- 11: begin//----------------------- WRITE INSTRUCTION ------------------------------------ LCD_RS <= 1'b0; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation RDY <= 1'b0; //Indicate that the module is busy if(SUBSTATE==0)begin LCD_E <= 1'b0; //Disable Bus LCD_DB <= LCD_DB; //Maintain Previous Data on the Bus STATE <= STATE; SUBSTATE <= 1; end if(SUBSTATE==1)begin LCD_E <= 1'b1; //Enable Bus LCD_DB <= DATA; //Data Valid if(!flag_250ns) begin //WAIT at least 250ns (required for LCD_E) SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin SUBSTATE <= SUBSTATE+1; //Go to next SUBSTATE flag_rst <= 1'b1; //Stop counting end end if(SUBSTATE==2)begin LCD_E <= 1'b0; //Disable Bus, Triggers LCD to read BUS LCD_DB <= LCD_DB; //Keep Data Valid if(!flag_42us) begin //WAIT at least 49us (required for operation to process) STATE <= STATE; //Maintain current STATE SUBSTATE <= SUBSTATE; //Maintain current SUBSTATE flag_rst <= 1'b0; //Start or Continue counting end else begin STATE <= 15;//STATE+1; //Go to next STATE SUBSTATE <= 0; //Reset SUBSTATE flag_rst <= 1'b1; //Stop counting end end end //--------------------------------------------------------------------------------------- default: begin//----------This is the IDLE STATE, DO NOTHING UNTIL OPER is set----------- LCD_RS <= LCD_RS; //Indicate an instruction is to be sent soon LCD_RW <= 1'b0; //Indicate a write operation LCD_DB <= LCD_DB; //Maintain Data Bus LCD_E <= 1'b0; //Disable Bus RDY <= 1'b1; RST_output <=1'b1; //Indicate that the system is ready to taking in data if(ENB==1)begin case(OPER) 0:STATE<=STATE; //IDLE 1:STATE<=10; //WRITE CHARACTER 2:STATE<=11; //WRITE INSTRUCTION (assumes 49us or less time to process instr) 3:STATE<=0; //RESET endcase end end endcase end endmodule |